1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) circuit and, more particularly, to a charge pump disposed in the PLL circuit.
2. Description of the Prior Art
Referring now to FIG. 6, there is illustrated a block diagram of a PLL circuit. In the figure, reference numeral 12 denotes a phase detector (PD), 14 denotes a charge pump (CP), 16 denotes a low-pass filter (LPF), 18 denotes a voltage controlled oscillator (VCO), and 20 denotes a frequency divider. Furthermore, reference character fo denotes a reference signal, and f denotes a PLL signal having a frequency obtained by division of the frequency of the VCO 18 by the frequency divider 20, *UP denotes a negative logical error signal (although a negative logical signal is generally designated by reference character marked with a line directly over it, the negative logical error signal is designated by the reference character UP with * just before it) furnished by the phase detector 12, DOWN denotes an error signal furnished by the phase detector 12, and VCP denotes a VCO control voltage for controlling the VCO 18.
In operation, the phase detector 12 compares the phase of the PLL signal f with that of the reference signal fo. Then, the phase detector 12 furnishes either the error signal *UP or DOWN according to the phase difference between the PLL signal f and the reference signal fo. Either the error signal *UP or DOWN is furnished successively within a period of time during which there exists a phase difference between the PLL signal f and the reference signal fo. The pulse duration of the error signal is proportional to the phase difference.
The error signal *UP or DOWN furnished by the phase detector 12 is applied to the charge pump 14. The charge pump 14 furnishes the VCO control voltage VCP for controlling the oscillation frequency of the voltage controlled oscillator 18 according to the error signal *UP or DOWN in cooperation with the low-pass filter 16. More specifically, the charge pump 14 supplies a charge to the low-pass filter 16 or alternatively extracts a charge from the low-pass filter 16 according to the error signal *UP or DOWN so as to cause the low-pass filter 16 to generate the VCO control voltage VCP.
The voltage controlled oscillator 18 oscillates to furnish a signal having a frequency which differs according to the VCO control voltage VCP furnished by the low-pass filter 16. The frequency divider 20 receives the signal and divides its frequency by n to produce the PLL signal f applied to the phase detector 12. In the state in which the phase detector 12 does not furnish the error signals *UP and DOWN, the PLL circuit is locked and therefore the phase of the reference signal fo is exactly coincident with that of the PLL signal f.
Referring next to FIG. 7, there is illustrated a schematic circuit diagram of the prior art charge pump. In the figure, the low-pass filter 16 is also shown together with the charge pump 14 because the charge pump 14 and low-pass filter 16 produce the VCO control voltage VCP in cooperation with each other as previously explained. In FIG. 7, reference character V.sub.DD denotes a voltage of a power supply.
The charge pump 14 shown in FIG. 7 has a CMOS structure with a PMOS transistor P31 having a gate to which the error signal *UP is applied and an NMOS transistor N31 having a gate to which the error signal DOWN is applied.
The low-pass filter 16 has a passive structure comprised of two resistors R1 and R2 and two capacitors C1 and C2.
In operation, when the charge pump 14 receives the error signal *UP furnished by the phase detector 12, the PMOS transistor P31 is switched on. As a result, the power supply is electrically connected to ground and therefore the VCO control voltage VCP is generated and furnished from a point between the resistors R1 and R2 of the low-pass filter 16. The waveform of the VCO control voltage VCP is defined by the power supply voltage V.sub.DD, ON resistance RP31 of the PMOS transistor P31, resistances of the resistors R1 and R2, and capacitances of the capacitors C1 and C2.
Referring next to FIG. 8, a graph shows an example of the waveform of the VCO control voltage VCP. When the error signal *UP is applied to the charge pump 14 at time t.sub.0, the VCO control voltage VCP begins to rise. Then, when the error signal *UP disappears at the gate of the PMOS transistor P31, the VCO control voltage VCP begins to descend. As can be seen from the figure, even if an enough time has elapsed since time t1, the VCP does not return to its previous value that it had at time t.sub.0 or an earlier time and has a voltage difference as shown in FIG. 8. This voltage difference controls the oscillation frequency of the voltage controlled oscillator 18.
Since the prior art PLL circuit is so constructed as mentioned above, it suffers the following disadvantage.
The performance of the PLL circuit can be evaluated with an eye to its locking speed and stability. The locking speed means the reciprocal of the time that elapses before the PLL is locked. The stability means the degree of resistance of the PLL to going out of the locking state caused by a disturbance such as noise. The locking speed is increased as the rate of change of the VCO control voltage VCP is increased. On the other hand, the stability is improved as the rate of change of the VCO control voltage VCP is decreased. That is, there is a trade-off relationship between the locking speed and the stability, with respect to the rate of change of the VCO control voltage VCP.
When the charge pump 14 shown in FIG. 7 receives the error signal *UP, it divides the power supply voltage V.sub.DD according to the phase difference, which is represented by the pulse duration of the error signal *UP, between the PLL signal f and the reference signal fo by means of the ON resistance RP31 of the PMOS transistor P3 and the resistors R1 and R2 so as to generate the VCO control voltage VCP. The capacitors C1 and C2 become charged by charges supplied by the power supply. Since the ON resistance RP31 of the PMOS transistor P31 is sufficiently small and the following inequalities EQU RP31&lt;&lt;R1, R2
hold, the VCO control voltage can be given by dividing the power supply voltage V.sub.DD using the resistors R1 and R2.
Accordingly, the variation of the VCO control voltage VCP is proportional to R2/(R1+R2). Since R2/(R1+R2)=1/(1+(R1/R2)), an increase in (R1/R2) reduces the rate of change of the VCO control voltage VCP and hence the stability is improved. On the contrary, a decrease in (R1/R2) increases the rate of change of the VCO control voltage VCP and hence the locking speed is increased. However, since the resistors R1 and R2 are passive elements, the ratio (R1/R2) in the prior art PLL circuit is set to a constant value. Therefore, the trade-off between the improvement of the locking speed and stability cannot be resolved.
As mentioned above, a problem with the prior art PLL circuit is that both of the locking speed and stability cannot be improved at the same time.